Name: CMOS Inverter Layout
Status: complete
Affiliation: 18-220 Electronic Devices and Analog Circuits Lab 3
Group members: Frank
Start: 2/9/2011
End: 2/9/2011
Description: Using L-Edit (layout editor), designed a minimal CMOS inverter using n-channel and p-channel transistors. The transistor depiction of an inverter is as follows:
We were given the constraints of λ = .5 uM, Z_n = 20 uM = 40 λ, and Z_p = 60 uM = 120 λ. In both channels, L = 2 (minimum possible L) because there were no additional constraints on it.
Lessons Learned:
-introduction to layout design in L-Edit
-minimal design rules
-using DRC to check whether or not I pass minimal design rules
-taking layout cross sections
-testing separate components helps identify which part of your layout is wrong - this applies to EVERYTHING, including unit testing, classes, modules, etc.
yes, that's a big X through our entire design...
designed whole layout in one shot, then used the DRC tool. frustration ensued.
finalized inverter layout
You'll want to extend those contacts all the way down one side. Contacts have a high resistance to them.
ReplyDeleteI can provide examples of layouts I did some years back and provide examples of my own. I wouldn't mind helping out.
Your PMOS shouldn't be that large and that close to your NMOS. Consider increasing the distance between transistors. Also, rotate your devices by 90 degrees so as to avoid a greater chance of latchup in the configuration you have.
Thanks for the comments! Sorry about replying so late, had a rough week with verilog.
ReplyDelete@contacts: I'll update that image, I went back after speaking to my professor and placed them along the side as you mentioned. How much does the resistance impact the charge distribution? If you have them too close will there be capacitance?
@layouts: Sure, I'd be interested in seeing some. I think layouts were a very small portion of our class as we're on circuit analysis now. Also, we used LEdit to do these, which is kind of old (it has to change windows to 8bit color display when we run it haha)
@P/NMOS location: We designed these while trying to minimize total area of the device. How would you normally go about that, since I believe the distance between the two areas isn't a standard design rule.
@asm developer:
ReplyDeletehow would you deal with lower p-sub mobility without the current sizing conditions? are you referring to using fingers instead of extending the width?
can you please tell me what is MOSFET specification.please tell me the p channel and n channel number
ReplyDelete